Techniques for protecting integrated circuits from large, undesirable current and voltage signals (e.g., ESD, EOS, etc.) are well known, particularly for integrated circuits employing a single power supply rail (hereinafter "power rail"). In single power rail systems, ESD and EOS protection circuitry (hereinafter "ESD circuitry") need only be provided between a single power rail and a reference power rail such as ground (hereinafter "reference rail"). More recently, multiple power rail applications such as mixed-voltage interface circuitry, dynamic random access memory (DRAM) circuitry and the like have necessitated ESD protection between multiple power rails as well as between each power rail and ground.
Many multiple power rail applications have the additional requirement that power rails must be able to be powered-up or powered-down in any sequence without generating wasteful or harmful voltage or current conditions between the power rails (i.e., a sequence independence or power-up/power-down independence requirement). For example, an interface circuit between a printer and a computer should prevent current flow between the computer and the printer when only one of the computer and the printer is ON.
One conventional technique for providing multiple power rail, sequence independent ESD circuitry is disclosed in commonly assigned U.S. Pat. No. 5,610,791 to Voldman and is described with reference to FIG. 1. Specifically, FIG. 1 shows conventional ESD circuitry 101 which comprises a first single-rail ESD circuit 103a connected between a first power rail (V.sub.DD1) and a reference rail (V.sub.SS) (e.g., ground), a second single-rail ESD circuit 103b connected between a second power rail (V.sub.DD2) and the reference rail (V.sub.SS), and an inter-rail ESD circuit 105 connected between the first and the second power rails (V.sub.DD1), (V.sub.DD2). As described below, each single-rail ESD circuit 103a, 103b produces a low impedance path between the single-rail ESD circuit's respective power rail and the reference rail (V.sub.SS) in response to an ESD impulse on the respective power rail so that the ESD impulse's energy is harmlessly dissipated (i.e., providing"single-rail" ESD protection). Similarly, the inter-rail ESD circuit 105 produces a low impedance path between the first and the second power rails (V.sub.DD1), (V.sub.DD2) in response to an ESD impulse applied therebetween so that the ESD impulse's energy is harmlessly dissipated (i.e., providing"inter-rail" ESD protection). A control connection 107 within the inter-rail ESD circuit 105 prevents the inter-rail ESD circuit 105 from dissipating current between the first and the second power rails (V.sub.DD1), (V.sub.DD2) in a sequence independent manner (as described below).
The first single-rail ESD circuit 103a comprises a plurality of p-channel metal-oxide-semiconductor field-effect-transistors (PFETs), specifically a first PFET 109 and a second PFET 111, and a first capacitor 113. The first PFET 109 has a source lead "S" and well lead "W" connected to the first power rail (V.sub.DD1), a gate lead "'G" connected to the reference rail (V.sub.SS), and a drain lead "D" connected to the gate lead "G" of the second PFET 111 and to the reference rail (V.sub.SS) via the first capacitor 113. The second PFET 111 has a source lead "S" and a well lead "W" connected to the first power rail (V.sub.DD1) and a drain lead "D" connected to the reference rail (V.sub.SS). The second single-rail ESD circuit 103b comprises a third PFET 115, a fourth PFET 117 and a second capacitor 119 similarly interconnected between the second power rail (V.sub.DD2) and the reference rail (V.sub.SS).
In operation, with the gate lead of the first PFET 109 connected to the reference rail (V.sub.SS) (e.g., ground), the first PFET 109 is ON and behaves as a resistor connected between the gate lead of the second PFET 111 and the first power rail (V.sub.DD1). The first PFET 109 and the first capacitor 113 thus form an RC discriminator (e.g., a low pass filter) such that the first capacitor 113 can charge quickly enough to track low frequency (e.g., D.C.) voltage changes on the first power rail (V.sub.DD1). Accordingly, absent a high frequency change in voltage on the first power rail (V.sub.DD1), the voltage present on the gate of the second PFET 111 and the voltage present on the source of the second PFET 111 remain approximately equal (e.g., VGS=0), and the second PFET 111 remains OFF. However, with the channel resistance R of the first PFET 109 and the capacitance C of the first capacitor 113 properly chosen, the first capacitor 113 is unable to charge quickly enough to track the high frequency voltage changes on the first power rail (V.sub.DD1) due to an ESD impulse. Accordingly, when an ESD impulse is present on the first power rail (V.sub.DD1), the voltage present on the gate of the second PFET 111 initially remains unchanged (as the first capacitor 113 charges toward the ESD impulse's voltage) while the source and the well of the second PFET 111 track the voltage of the ESD impulse. The gate-to-source voltage of the second PFET 111, therefore, exceeds the second PFET 111's threshold voltage and the second PFET 111 turns ON. With the second PFET 111 ON, a low impedance path is created between the first power rail (V.sub.DD1) and the reference rail (V.sub.SS).
The second PFET 111 remains ON until the first capacitor 113 charges to a voltage sufficient to turn OFF the second PFET 111 or until the ESD impulse is dissipated, whichever occurs first. If the charging time for the first capacitor 113 is sufficiently long (as set by the RC time constant of the current path to the first capacitor 113, which is set by the first PFET 109 and the first capacitor 113), the second PFET 111 will remain ON long enough for the ESD impulse to be harmlessly dissipated (e.g., to ground). The second single-rail ESD circuit 103b behaves identically with respect to the second power rail (V.sub.DD2).
The inter-rail ESD circuit 105 comprises a fifth PFET 121 and a first PNP transistor 123. The fifth PFET 121 has a gate lead "G" connected to the second power rail (V.sub.DD2), a source lead "S" connected to the first power rail (V.sub.DD1) and a drain lead "D" connected to the well "W" of the fifth PFET 121 and to the well "W" (e.g., the base) of the first PNP transistor 123 via the control connection 107 (forming a node 107'). The first PNP transistor 123 has a collector lead "C" connected to the first power rail (V.sub.DD1) and an emitter lead "E" connected to the second power rail (V.sub.DD2). For reasons described below, the fifth PFET 121 is sized much smaller than the first PNP transistor 123 and the first PNP transistor 123 is symmetrically doped.
When an ESD impulse is present across the first and the second power rails (V.sub.DD1), (V.sub.DD2), the fifth PFET 121 has little affect on the response of the first PNP transistor 123 (due to its small size relative to the first PNP transistor 123). For instance, with an ESD impulse induced on the first power rail (V.sub.DD1) relative to the second power rail (V.sub.DD2), the collector of the first PNP transistor 123 is pulled high rapidly via the ESD impulse and the first PNP transistor 123's collector-base junction is forward biased while the first PNP transistor 123's emitter-base junction is reverse biased. The first PNP transistor 123 thereby is turned ON, current flows from the first power rail (V.sub.DD1) to the second power rail (V.sub.DD2) and the ESD impulse is harmlessly dissipated. Base current is "forced" through the fifth PFET 121 during dissipation of the ESD impulse.
Similarly, with an ESD impulse induced on the second power rail (V.sub.DD2) relative to the first power rail (V.sub.DD1), the first PNP transistor 123's emitter is pulled high rapidly via the ESD impulse and the first PNP transistor's emitter-base junction is forward biased while the first PNP transistor 123's collector-base junction is reverse biased. The first PNP transistor 123 thereby is turned ON, current flows from the second power rail (V.sub.DD2) to the first power rail (V.sub.DD1) and the ESD impulse is harmlessly dissipated. Again, base current is forced through the fifth PFET 121 during dissipation of the ESD impulse.
The primary role of the fifth PFET 121 is to provide sequence independence between the first and the second power rails (V.sub.DD1), (V.sub.DD2). For example, if the first and the second power rails (V.sub.DD1), (V.sub.DD2) are initially at ground potential, a typical power-on sequence might comprise raising the first power rail (V.sub.DD1) to a first voltage (e.g., 2.5 v) prior to raising the second power rail to a second voltage (e.g., 3.3 v). With the first power rail (V.sub.DD1) at the first voltage while the second power rail (V.sub.DD2) is grounded, the fifth PFET 121 is turned ON and the node 107' is raised (e.g., charged) to the first voltage.
The base-collector junction of the first PNP transistor 123 is unbiased and the base-emitter junction of the first PNP transistor 123 is reverse biased. Accordingly, the first PNP transistor 123 remains OFF.
When the second power rail (V.sub.DD2) is raised to the second voltage (e.g., 3.3 v), the fifth PFET 121 turns OFF. The node 107' charges from the first voltage to approximately the second voltage minus the forward voltage of the first PNP transistor 123's base-emitter junction and the first PNP transistor 123 remains OFF. If the first power rail (V.sub.DD1) thereafter is grounded, the first PNP transistor 123's base-emitter junction remains insufficiently forward biased for the first PNP transistor 123 to turn ON. Accordingly, the first and the second power rails (V.sub.DD1), (V.sub.DD2) may be powered-up or powered-down in any sequence without generating wasteful or harmful voltage or current conditions between the first and the second power rails (V.sub.DD1), (V.sub.DD2).
The conventional ESD circuitry 101 of FIG. 1 provides excellent ESD protection for integrated circuits employing power rail voltages of at least 2.5 volts (e.g., V.sub.DD1 =2.5 v, V.sub.DD2 =3.3 v, etc.). However, for circuitry employing lower voltage power rails (e.g., V.sub.DD1 =1.8 v, V.sub.DD2 =2.5 v, etc.), the "ESD trigger voltage" required to turn ON the first PNP transistor 123 (e.g., about 9 volts) is too large to prevent damage to the smaller dimension transistors (e.g., MOSFETS having lower snap-back voltages) typically employed within lower power rail voltage integrated circuits. Because there exists no easy method for reducing the ESD trigger voltage of the first PNP transistor 123 the conventional ESD circuitry 101 of FIG. 1 cannot be scaled for use with lower power rail voltage integrated circuits.
In addition to lacking scaleability, the conventional ESD circuitry 101 also is difficult to tune. Specifically, gate capacitance contributions from the second PFET 111 affect the RC characteristics of the low pass filter formed from the first PFET 109 and the first capacitor 113, and must be considered during the selection of the first capacitor 113. Similarly, gate capacitance contributions from the fourth PFET 117 affect the RC characteristics of the low pass filter formed from the third PFET 115 and the second capacitor 119, and must be considered during the selection of the second capacitor 119. The second and the fourth PFETs 111, 117, therefore, cannot be optimized without affecting the selection of the first and the second capacitors 113, 119, and vice versa. Further, many designers prefer non-PFET based circuit designs due to the threshold-voltage dependence associated with PFETs that can lead to high temperature thermal runaway in PFET based networks.
Accordingly, a need exists for a method and apparatus for providing scaleable ESD protection with predictable RC characteristics that ensure proper ESD impulse dissipation. Such a method and apparatus will alleviate the need for ESD circuitry redesign for each successive generation of lower voltage circuitry.